The present invention relates to a semiconductor integrated circuit device and a semiconductor memory for such uses as a memory device with logic function constituting a buffer storage device (buffer memory device) for computers.
In the related art, there exists a prior art memory device with logic function having a plurality of RAM (random access memory) macrocells and gate arrays. There are digital processors such as a computer having a buffer storage that comprises the above memory device with logic function.
The memory device with logic function having multiple RAM macrocells and gate arrays is illustratively discussed in such publications as U.S. patent application Ser. No. 07/198,311, filed and assigned to Hitachi, Ltd. by Isomura et al. on May 25, 1988. The gate arrays of this prior art memory device comprise ECL (emitter coupled logic) circuits based on bipolar transistors for high-speed operation. The inventors found that this construction hampered efforts to reduce the power dissipation of the memory device and to enlarge the scale of circuit integration thereof. This has resulted in long delay times required for signal transmission and hence relatively low speeds of operation. The inventors' investigation further revealed that constraints on the circuit integration of the memory device with logic function kept the sharing of functions between the memory device and other devices from being optimized. The resultant long critical path of computers has imposed limitations on the cycle time thereof.